1. Field of the Invention
The present invention relates to a system including a number of memory modules and a chip set memory controller having a data strobe mask function.
2. Description of the Conventional Art
Generally, the DDR method is directed to a method for reading a data from a memory apparatus based on a rising edge and falling edge of a master clock signal and writing the data into the memory apparatus. In addition, in the DDR method, in order to obtain a high speed operation margin of the memory apparatus, a data strobe signal is used based on an echo clock.
The data strobe signal generates an echo clock in the same manner as the output of a first data output buffer when outputting the data, and in the chip set memory controller, the data are read in response to the data strobe signal.
In FIG. 1, reference numerals 12 through 18 represent a memory module containing a plurality of memory devices. Reference numeral 10 represents a chip set memory controller. Each of the memory devices is a dual in-line memory device. Therefore, the memory module represents a dual in-line memory module. As the memory device, a SDRAM is generally used. Preferably, the DDR SDRAM is used therefor.
The chip set memory controller outputs a mask clock CLK, and the master clock is applied to each of the dual in-line memories 12, 14, 16 and 18. Each dual in-line memory module inputs and outputs a data DQ in synchronous with the master clock. The data DQ of FIG. 1 represents a case that the data is read from the dual in-line memory module.
The DS of FIG. 1 represents a data strobe signal.
If a data strobe signal is not provided, the time required for the data outputted from the dual in-line memory module 12 which is nearest the chip set memory controller 10 to reach the memory controller is different from the time required for the data outputted from the farthest dual in-line memory module 18 to reach the memory controller. In addition, the case where the data is applied from the memory controller to the memory module is the same as the above-described case.
Meanwhile, when the data strobe signal is used, since the time required until the data is outputted from each dual in-line memory module is the same as the time required until the data reaches the memory controller, it is possible to implement a high speed operation of the memory.
However, in the case of the data strobe method, there is a problem that the output data mask(DQM: DQ MASK) may not be used, which is an important function of the SDRAM.
Namely, in the read mode, when operating the output data mask (DQM), the conventional SDRAM does not selectively control the data strobe signal. In the write mode, the same problem occurs.
The above-described problems will be explained in more detail with reference to FIGS. 2A and 2B.
FIG. 2A illustrates that there is not a data strobe mask function. Each memory module includes a plurality of DDR SDRAMs. Each of memory modules 20 and 22 includes the same number of DDR SDRAMs and co-uses a data bus DQ, a data strobe DS, and an output data mask DQM. The output data is formed of 8-byte.
The operation of FIG. 2A will be explained with reference to FIG. 2B.
In FIG. 2B, it is assumed that the burst length is 8.
Reference character CLK represents a mask clock, DQ_M1 represents a data outputted from a first memory module 20, and DQ_M2 represents a data outputted from a second memory module 22. In addition, reference character DQM represents an output data mask signal, QS_M1 represents a data strobe signal outputted from the first memory module 20, QS_M2 represents a data strobe signal outputted from the second memory module 22, and QS BUS represents an output data strobe bus.
The data are accessed from the first module 20 for the first through third periods of the master clock, and the data of the second module 22 are accessed for the fourth and fifth periods of the clock.
The data outputted from the first module 20 are masked in accordance with an output data mask (DQM) signal. However, in this case, while the data strobe QS_M1 from the first memory module 20 continuously maintains an operation state, the data strobe QS_M2 from the second memory module 22 is enabled. Since the memory modules 20 and 22 co-use the output data strobe bus QS BUS, a bus contention may occur at the portion "A".
Namely, in the conventional art, when operating the output data mask DQM, it is impossible to selectively control the data strobe signal.